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First Pass 90nm Silicon Success
Multi-media Processor
Huge Cost Reduction on PCM Chip
Low Power Design
12 Million Gate Count Design
Optical Shrink Technology
WCDMA Base Station
ESD Production

 

Success Story: WCDMA Base Station

Chip Function
Wireless application
 
Design #1 Summary
  • Technology: UMC 0.18um + 1 poly 6 layer metals
  • Gate counts: 4M + 151 Macros (3.9M bits memory)
  • Frequency: 64MHz
  • Die size: 12.8x12.8 mm^2
Design#2 Summary
  • Technology: UMC 0.18um + 1 poly 6 layer metals
  • Gate counts: 3M + 206 Macros (3M bits memory)
  • Frequency: 64MHz
  • Die size: 10.6x10.6 mm^2
Challenges
  • Floorplan methodology (handling more than 150 macros)
  • Hierarchical design planning to manage the complexity of multimillion-gate designs and achieve timing closure
  • Fast turn around time: 6 weeks schedule from get final netlist to tape-out.
  • 5% IR drop, low IR drop implementation for high power consumption 3.5W.

A big telecom company adopted EE Solutions multi-million-gate count design flow to tape-out two 4 million gate wireless telecommunication application designs with 0.18um process within 33 days in year 2002. The designs included more than 150 hard macros and the IR drops are within 5%.

EE Solutions were a back-up alternative against a famous multi-national ASIC company. EE Solutions formed a task force for the project and closely controlled the schedule by our superior project management team. EE Solutions taped out the 2 ASICs for the customer in a short period of time and the samples were tested while the NMC company who started the project one month earlier still far away from taping out the chip.

 
   
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