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Success Story: Huge Cost Reduction Cases

#1	66% Cost Reduction on PCM Chip
#2	50% Cost Reduction on Super I/O case
#3	10 Folds Cost Reduction on Microphone Pre-amplifier case
#4	Huge Cost Reduction on Telecom case

#1 66% Cost Reduction on PCM Chip

Chip Function
Power Charger - PI TNY264 compatible - Fairchild FSD200 compatible

Type of engagement
Pin-to-pin compatible

Design Summary
Years of joint development effort with high voltage foundry (650V+) Provide much cost effective solution compared to North America based IC offerings (Power Integration, Fairchild, etc.)
EES Value to Customer
Cost reduction by 66% !

#2 50% Cost Reduction on Super I/O case

Chip Function
Super IO for Industrial PC

Type of engagement
Multiple ASSP integration LPC to ISA (W83626F) Super IO (W83627) Add microcontroller for debug and security
EES Value to Customer
Cost reduction by 50% ! Market differentiation – customized solutions Product protection (no off-the-shelf IC supplier)

#3 10 Folds Cost Reduction on Microphone Pre-amplifier case

Chip Function
Microphone Pre-amplifier

Type of engagement
Customized ASIC
EES Value to Customer
Years of accumulated design experience with X-fab Partnership with talented design team to meet customer’s design requirements
Customer justification
Cost reduction by ten folds ! Further cost reduction with next design migration to another fab

#4 Huge Cost Reduction on Telecom case

Chip Function
Telecom phone switch

Design Summary
Technology: UMC 0.35um + 2 polys 3 layer metals Cell counts: 50K + 6 Macros
Design Challenges
Embedded regulator (5V to 3.3V) without external capacitor for peak 1A within 5% low drop output (LDO) IR drop was improved from 50% to 5% in 1A without additional metal overhead Customize IO cells and full chip ESD design, sustain ESD up to 6KV Customize Standard cell lib for special corners Significant cost reduction by using 0.35um process instead of 0.5um Region base placement approach to deal with asynchronous latch base design Yield improved from 81% to 98% Solve existing latch up problem
ROI
US$3-5M per year for 3 years and could be bigger!
EE Solutions provided its process porting capability to a big Asia telecom company to port a 0.5um design to 0.35um process to shrink the die size significantly. As a result, the customer reduced their cost dramatically by shipping multi-million chips per year. For the porting purpose, EE Solutions utilized the 0.35um library created internally including standard cells, I/O cells and memory macros. A 5V to 3.3V regulator was also created internally in order to transform the 5V power from customer’s system board to 3.3V, hence the 0.35um core logic in the ASIC could be powered. Even it was a 0.35um design which normally power is not an issue, EE Solutions still ran the power integration tool as standard procedure before the tape-out to achieve the IR drop tolerance. The ASIC’s final testing guardband was taken care carefully. As a result, the test patterns screened out the no-good parts while kept the good parts with better accuracy. The cost reduced due to the raise of the yield rate contributed by the new set of test patterns.