Chip-design solutions: Q&A with Jim Su and Hugh Huang of EE Solutions

Chris Hall, DigiTimes, Taipei - February 14, 2006

Semiconductor design-service companies face any number of challenges as chip complexity rises in direct proportion to time-to-market pressure. Couple that with the industry's move to deep submicron, and it soon becomes clear that IC design is not a business for the faint-hearted. Headquartered in Taiwan's Hsinchu Science Park (HSP), EE Solutions is confronting the challenges with a commitment to design methodology, a determination to generate its own IP, a consistent focus on strategic markets and a sophisticated understanding bred of long experience in the industry.

DigiTimes.com spoke with EE Solutions president Jim Su and sales VP Hugh Huang about the company's business model, the issues now facing the chip-design industry and the company's strategy for success.

Q: I understand EE Solutions has a large portfolio, leaning more towards structured-ASIC solutions. How would you characterize structured ASICs? Why are they particularly significant?

Huang: A structured ASIC is halfway between an FPGA and a custom ASIC. With an FPGA, you don't need to do any back-end design. Once you have the RTL code, you can start to compile it into the FPGA. There is no need for mask production, nor do you need to do place and route or other back-end processes. But with a custom ASIC, once you have generated the RTL code you then move on to synthesis, and then you have to move on to back-end design – floor-planning, place and route, checking the timings, and so on, until finally the design is ready for the mask house. All of that takes time. It is very time-consuming, and manufacturing the mask set is very costly.

The structured ASIC is in the middle of these two extremes. With a structured ASIC, you only have to do place and route for maybe the last two or three layers of the mask. That means you save both time and money. The rest of the mask layers have already been prepared at pre-layout. So, for example, with a 0.l8-micron design, you would normally need something like 29 or 30 layers of mask. With a structured ASIC, the idea is that 25, 26 or 27 layers of the mask, let's say, have already been prepared, already manufactured at the pre-layout stage. Then you design the last five layers. A structured ASIC can save you 25 layers of the mask costs, as well as the manufacturing cost of the first 25 layers of the IC.

However, a structured ASIC also has some constraints. You cannot make your die as small as you would want for a custom ASIC because some of the design has already been pre-laid out, and that cannot be changed. On the other hand, that may be preferable to using an FPGA because with an FPGA, you have almost no flexibility to shrink the die size, and FPGA dice are usually quite large.

What this all means is that structured ASICs are suitable for ICs that are not going to be produced in high volume, but where you do not want a high unit price. In general, the unit price of a structured ASIC is between that of an FPGA and a custom ASIC. For example, if the customer only needs 200 or 500 ICs a year, then they would probably opt for the convenience of an FPGA. Nevertheless, that's a relatively expensive option; an FPGA might cost you US$1,000, US$5,000 or US$10,000 per unit. If instead you chose to go with a custom ASIC, your unit cost might only be five or ten dollars.

A structured ASIC would cost you in the range of US$25 to US$50, so the cost is low. If you want a solution that is a compromise between cost and quality, then a structured ASIC is a good choice. Otherwise, you will need to go with either a custom ASIC or an FPGA.

Q: How does the production timeline of structured ASICs compare with that of custom ASICs and FPGAs?

Huang: Well, let's say you have finished the front-end design; let's start from that point. Whichever solution you choose, you'll need to start with the RTL code. Once you have the RTL code, it would probably then take you a week or so to have a finished FPGA. But for a custom ASIC, it would probably take you a couple of weeks to do the back-end design. It would probably take you another one and a half months for wafer fabrication. Then it would take you another 10 days for packaging. So by the time you finally have your finished custom ASIC ready to test, it would probably take you about three and a half months. But for a structured ASIC, because you only design five layers of the mask, and you only manufacture the last five layers of the IC, it would probably take you only three weeks, maybe, to have the complete IC.

Q: That is quite a marked reduction in time, and everyone tells me time is money.

Huang: They are correct.

I think another important point you need to consider is the market for structured ASICs. I think that the structured ASIC is most suitable for big system companies. For example, if you are manufacturing medical equipment, or if you are manufacturing mainstream printers, and your production volumes are in the millions, then you will need to go with a custom ASIC. But if you are only manufacturing between 10,000 and 50,000 ICs a year, then an FPGA solution would be too expensive, and you would need to go with a structured ASIC.

Q: How does that fit with the services supplied by EE Solutions? Would it be accurate to say you are a company that specializes in structured ASICs?

Huang: Well, we have different kinds of customers. We have telecommunications customers; we have customers active in the consumer space, and we have customers who are in the computer industry. That means we need to be able to offer a complete spectrum of products and services for our customers. If they are a consumer-products company, perhaps they have one specific IC that is not in very big demand and only available at a high price. In that case we can provide a structured-ASIC solution, and that will allow them more choices. If, on the other hand, they want a unique solution, then we could also design a custom ASIC for them.

For companies who choose the structured-ASIC option, we represent a US company, ChipX, that specializes in structured ASICs. EE Solutions is the Taiwan representative of ChipX.

Q: EE Solutions seems to be a very US-influenced company. Would you agree?

Su: I would say so. I worked for Cadence in the US, for ten years. Then I moved back to Asia, still working for Cadence. I worked for Cadence Taiwan for four years before founding this company. Most of the founding members of the company have a background in EDA, so we have a strong background in design methodology, including of course design for test (DFT), design for manufacturing (DFM), design for yield (DFY) and so on.

Within Cadence, there had been a services group, the Consulting Services Group (CSG). This group tried to assist customers with setting up their QA environment. In 1995, CSG acquired Unisys, which had a fab and a design team in the San Diego area, with the aim of growing CSG and enabling it to offer spectrum services. By spectrum services I mean a complete range of design services.

With the acquisition, CSG grew to have 19 design centers around the world, all able to provide design services. This design-services group grew to have over 4,000 employees, and Cadence decided to spin it off as a separate company, Tality. This was, in fact, the first IC design-services company to come into existence in North America, and Tality offered an IPO in the late 1990s.

However, Tality didn't do well, for a number of reasons. They had offered pure design services to their customers, but finally the venture wasn't successful. Today Cadence only retains a small group for provision of ASIC design and EDA services.

Basically, I believe, Tality failed because of the pure design-service model. Pure design service only results in products that can be sold once. Whether the non-recurring engineering expenses (NREs) are high or low, revenue from pure design service is always limited. It's extremely difficult to make it successful. It does not result in products that are repeatable, by which I mean, products that go through repeated manufacturing cycles over time.

This is Part I of a four-part interview. Part II will appear on 15 February.

Jim Su, president, EE Solutions Inc
”Most of the founding members of the company have a background in EDA, so we have a strong background in design methodology.”

Hugh Huang, sales VP, EE Solutions

Q: How would you characterize EE Solutions as a company within semiconductor design services? What are your strengths, what are your technology specializations?

Su: I think a design-service company needs to provide a full range of services, including ASIC/turnkey services, where the design company also oversees the manufacturing of the chips and their delivery to the customer. Production and sale of those chips are then repeatable, and revenues can be larger and more long-term. Learning from the Tality lesson, I formed EE Solutions with the ASIC/turnkey model in mind.

We sell the chips we design mainly to system companies. If we sold them to other IC companies, we would inevitably be competing with our own customers, so the majority of our designs and turnkey agreements are with system companies.

EE Solutions offers two types of chip design. One is designed down to an FPGA, at which point it is targeted for volume production. However, it is very costly to take an FPGA into volume production, so we convert the design to an ASIC. That's one service that we offer, and it's quite common for us to provide that FPGA-to-ASIC service. It's quite common for the system companies to design their chips using FPGAs, but if that design then requires mass production, with possibly several hundred thousand units required to satisfy market demand throughout the complete lifecycle of the chip, then it's better to convert the design to a custom ASIC or a structured ASIC. That will save costs, and that's one of the services we provide.

EE Solutions also provides another type of service, one where the customer requires a feature or set of features already built into a commercial IC. Let’s say, however, that for one reason or another, the customer is unable to obtain the IC as an off-the-shelf item. In that case, they can come and talk to us and explain their needs and the specifications they require. We will then see if we can provide the design and implement the chip.

Both of these models are very normal within the IC-design industry; both are very common to the IC market. However, we have a third type of business that we can offer the system companies. If a chip is in volume production, and a system company needs a few million units per year, but they can only purchase that chip from the large IDM companies, they may want to cost down by obtaining a pin-to-pin compatible chip from another source. In that case, we can be the design source for the pin-to-pin compatible replacement. In other words, we supply basically the same chip, avoiding, for the customer, the high prices charged by the large IDMs, who are typically selling at a very high margin, typically 70-80%.

We provide this service for several of the large system companies, including UT Starcom, Samsung and Huawei. They will indicate to us, usually via their website, the specifications required for that chip, and we then design it. The beauty of this model is that it's the customer who then verifies the chip. We undertake testing of the chip once it has been packaged, but it's the system company who then has to design in and verify the chip.

These three models represent our primary business, and I believe that in today's market you have to have a design company that is willing to help the system companies in this way. A company such as Samsung is very large and probably ships several million units of a chip per month. The system house, on the other hand, may only sell several hundred thousand products per month. They must either buy the their chips from Samsung or design and make the chips themselves. For the system houses, purchasing from Samsung is too costly, so they need to find a company such as EE Solutions, one that is able to make the IC for them, following an FPGA prototyping stage. Generally, there is a lot of demand for taking a chip that has been successfully implemented in FPGAs to a finished ASIC.

Q: So you are in fact involved in a very successful business model? There is a lot of demand for your services?

Su: Basically, yes. Of course we cannot design and make all the ICs that are offered by the large IDMs. We have to specialize. We have to have a platform, and we have to have a design methodology.

On the other hand, we cannot design every IC from scratch. That means it is an absolute necessity for us to have silicon-proven IP. Having a certain piece of IP enables you to do certain designs. And once you have the IP and the design methodology, you then need the resources to implement the chip in silicon. All three of these elements are important.

Q: And you provide all three?

Su: Well, with design methodology, we adopt the EDA methods and tools of companies such as Cadence and Magma. With the IP, we generate a good deal of it ourselves. We customize some of it ourselves, and we also leverage some from external IP providers. For wafer fabrication, again we partner with companies such as UMC, TSMC, Chartered, SMIC or He-Jian, although we are not associated with any one particular foundry. We are quite different from a company such as Faraday, which provides design services for UMC, or Global Unichip, which designs chips for TSMC.

Q: So EE Solutions is capable of providing a complete range of design services, but as you pointed out, the one that brings in the least revenues is pure design, where there is no repeatability. Can you specify exactly what you mean by repeatability?

Su: By repeatability I mean that the same chip could be produced over several years, from a single design. For example, we designed and made a chip for a telecoms company in China, in 2001. The company continued to use that chip and place repeat orders for it until 2005. That's what I mean by repeatability. A single-chip design could result in recurring revenue over several years.

That's quite different from what happens with the kind of pure-design model operated by Tality. With the pure design model, the NREs you receive may amount, quite possibly to US$1 million, but your investment is also very high. There was one occasion when EE Solutions engaged with a customer to do that kind of project, and the NREs totaled more than US$1 million. People asked me if I had made money, and I told them no. The NREs sounded like a lot of money, but you have to consider what I had to invest in EDA tools. And the project may have taken ten people, say, half a year to complete. Their salaries also have to be factored in. So, in fact, I invested a great deal of money and resources in the project, and all I received was a million dollars.

Now, if you look at the other type of business model, ASIC/turnkey, let's say the NREs may only amount to US$100,000 – much less than for a million-dollar project. But once the chip has entered the market, I continue to supply the chip for four years. So imagine how much money I will make if every year I supply three million pieces. By the end of four years I will have pulled in US$10 million. That's considerably more than you would generate from a single pure-design project. This explains the problems of Tality when they tried to make money in the design business.

Don't get me wrong. When I was with Cadence, I tried to negotiate with TSMC for ASIC/turnkey services, on behalf of Cadence. And TSMC said, “OK, it's possible we would like to have Cadence as our design-service partner, but in return, we would prefer that Cadence uses TSMC exclusively, that we are their only foundry partner.” But Cadence couldn't accept that arrangement because most of their customers were companies such as Motorola and Infineon, companies that already owned their own fabs. Their attitude was that if they worked with TSMC, TSMC would, in the meantime, be working with these other Cadence customers, and inevitably, at some point, there would be a conflict of interest.

Q: I understand your business model also includes the provision of process-migration services. How does that work?

Su: We offer process migration service where, for instance, an IC company might be providing its products at 2 microns, but the design teams that could handle that kind of technology are all gone. They've been phased out. In that kind of case, we can supply some form of migration, to help the customer. This type of customer does have GDS technology, so we supply, for example, a GDSII direct shrink from 2 to 0.25 or 0.35 micron. Then we can send it to TSMC or to UMC or wherever, for fabrication.

There is one more business model we operate. I explained to you what exactly is the difference between ourselves and, say, Faraday and Global Unichip. In their case, they will handle all of the design for the foundry, including RTL code, GDSII, and so on, until the chip is ready for tape-out. (This is for UMC, in the case of Faraday, and for TSMC in the case of Global Unichip.) My problem is that I need to see if there is some way I can compete head-to-head with these two design-service houses.

Let's say that in that type of business there is a customer who goes to TSMC for fabrication, but faces strong cost-down pressure. Let’s say the customer comes to me for assistance. In that kind of case, I may be able to help them migrate their design from say 0.35 micron to 0.18 micron, which will result in significant cost reduction. Again, that’s a type of process-migration model. In some cases. I may be able to help them migrate the design from say TSMC to UMC or some other fab. Again, that’s a type of process migration, one that helps customers meet their cost-down objectives.

Q: What would you say is your key technology specialization?

Su: We have to have a very strong methodology as the foundation of our design, and in our case we have a very strong background in EDA. That background enables us to automate our design flow by putting together whatever is available in the market. That's why we combine tools from Cadence, Magma, Mentor and others to develop our own design flow. If, as in the past, I was working for an EDA company, I would be forced to use only that company's tools. The problem would be that those are not the most highly automated tools available in the market.

At EE Solutions, of course, we operate independently of the EDA companies, so we don't have that kind of constraint. That means we can pick the best and most advanced tools.

Q: You operate independently of the EDA companies, but I get the impression that you work quite closely with Magma. How would you characterize your relationship with Magma?

Su: As I mentioned before, we are not under any constraint to use the tools from just one EDA company. We like to use the most cost-effective tools available in the market to meet customer requirements.

In the late 1990s, we originally used Cadence's tools, but we found the tools had limitations that would not allow us to meet customer requirements. As a result, we decided to use tools from Magma. At that time, around 1991, no other company in Taiwan was using tools from Magma. Very few companies had even heard about Magma. But we obtained a very strong commitment from Magma, and we became their distributor in Taiwan. We worked with Magma's R&D team, at their headquarters in Cupertino, to deliver a ten-million gate-count network processor. At that time, ten million was regarded as a very large gate count. By working closely with Magma's R&D team, eventually we were able to deliver the design to the customer. That’s basically the background to the cooperative relationship between the two companies.

Nevertheless, two years prior to that, Cadence had offered a very good floor-planning tool, called First Encounter. We adopted that product, FE Encounter, but otherwise worked with Magma's tools. We continue to explore new tools, when they become available, and we look at all aspects of the design issues involved.

And of course when you start working on deep-submicron designs, you come up against many unexpected problems. You may have signal-noise issues; you may have power issues; you may have integrity issues. Once you have addressed these issues, maybe you have design-for-manufacturing (DFM) and design-for-yield (DFY) issues. Possibly you fail to achieve timing closure. You have to address all of these issues, to ensure that you have right-first-time silicon.

What can we do to meet these challenges? Sometimes we develop design utilities ourselves. For example, we have developed our own tool to enable checking for cross-talk. If this kind of tool is not available in the market, we have to develop it ourselves. That’s not always very efficient, but we do need some type of technology that will ensure the success of the design. The alternative is to talk to some of the rising stars of the EDA industry, in Silicon Valley. That’s how I first made contact with Magma. In 1999, no one had even heard of Magma, but we dared to work with them and tackle the very difficult design challenges we were getting from our customers.

Q: So if you work with a good, successful start-up, maybe you can get a good product, but at a lower price?

Su: Yes. And that can be your back-up solution. For example, I’ll use the flow we now have, whenever I’m working on a design, but at the same time I’ll use another tool as a benchmark. If the result is significantly improved, perhaps that means we should switch to that tool for that type of particular design.

Q: Currently, there’s a lot of discussion in the industry about implementing DFM and DFY. Have you come to any conclusions about how best to do this?

Su: There are two ways to look at DFM and DFY. One is from the point of view of the foundry. There it’s a question of improving the yield by improving the process. The second point of view is that of design. It’s essential to consider DFM and DFY in the early stages of the design cycle, rather than wait until you’re close to tape-out.

There’s a bunch of start-up companies in Silicon Valley who are trying to address this issue. Their conclusion is that you have to either work on DFY and DFM very early in the design cycle or work with the foundry with the objective of improving yield.

Q: Exactly how early in the design cycle could you start to incorporate DFM?

Su: Our approach is to start in the RTL to GDS phase, so when you do the RTL coding you need to take DFM and DFY into consideration. This requires greater tolerance of variations in the manufacturing process, in order to achieve faster timing closure. This is particularly the case at deep submicron because here, variations in manufacturing will have a greater impact. The sensitivity of the design to the manufacturing process is very significant when you’re designing on a nanometer scale. Usually, at 2 microns or 1 micron or 0.35 or 0.25 micron, there won’t be any problem. But when you get into deep submicron, 0.18 and 0.13 micron, you start to have power, noise, integrity and ESD issues – any or all of those. So today, we address the issue of yield after we have completed the GDS stage. At 0.18 micron you can try to fine-tune your process, but when you start to work on a nanometer scale, as we are today, that approach won’t work.

Q: You indicated that tweaking the manufacturing process won’t necessarily enable successful designs at deep submicron. You also hinted that the reason why that approach won’t work is that there is a very high level of unpredictability at deep submicron. Am I understanding you correctly?

Su: Yes. Our response is to try to minimize the impact of the issue of manufacturability, the challenge of manufacturability at that scale.

From the point of view of our technology, we are continuing to innovate, while also implementing a very solid design methodology, to minimize the difficulties and challenges of nanometer-level designs. And we are also continuing to develop partnerships with some IC vendors, to develop the IP we need for deep submicron. But I want to emphasize that when we form those partnerships, we target certain specific markets. It’s not the case that we are going after every market segment.

Basically, there are two markets in which we would like to be involved. One is wireless communication, and specifically wireless LAN, and that also means MIMO and WiMAX. These are all areas where we are now engaging with customers. For example, we have a silicon-proven analog-to-digital converter (ADC), and the same ADC can be used for wireless LAN, in MIMO implementations, for WiMAX, and even in HDTV. That’s also an example of what I mean by repeatability – designs that can be repeated across a range of product applications.

An SoC can offer similar opportunities. An SoC will incorporate standard functionalities, such as memory, often a microprocessor, and possibly an analog-to digital/digital-to-analog converter (AD/DA), but you will also have, as a design company, some type of critical IP that enables you to complete the design.

So that’s our position, when we develop our technology. We start by building a very strong design methodology. Then we develop critical IP, for some very critical aspect of the design, and that enables us to develop the chips our customers and our target markets require. One of those markets is wireless, and another is digital entertainment. Wireless is a huge field, so we have to be selective. We don’t want to touch the videophone market, for example. That’s far too complicated, so we leave that one to Mediatek, or to TI, or whoever wants to do it. We only become involved in certain specific markets.

Another area where we can be involved is digital entertainment. You’ve got to have audio codecs, video codecs, and so on. So we have these critical pieces of the design, or perhaps a single piece, that enables us to do the design for our customers. If you want to understand our approach to design, there are two things we emphasize: a strong foundation in methodology; and critical IP that enables us to develop chips for customers.

Q: Do you ever sell IP?

Su: No. We develop it, but we don’t sell it.

Q: There’s not really a market for IP?

Su: If you look at the IP-design business, there’s really only one IP vendor that has managed to make an IPO, and that is ARM. Apart from ARM, most of them have either died or barely managed to survive. Only ARM has managed an IPO. IP is not a good business to get into. You can sell IP and do business that way, but it’s not scalable.

This is not a technology problem. The technology barrier is not really all that high. Let’s take USB 2.0 for example. Two years ago, you could sell a USB 2.0 chip design for US$300,000. Today, the same design would only fetch US$30,000. What happened is that people saw how profitable it was to design for USB 2.0. Their reaction was to get in on the act, and that had the effect of driving down prices. In the case of USB 1.1, I can’t even charge for it. Now, a USB 1.1 physical layer, for example, I give that away free to customers. Today, it wouldn’t be possible to sustain a chip-design operation based on meeting demand for USB chips. Of course, some companies will respond by developing their own niche specialization. They may decide to move to wireless USB, for example.

Another problem is collecting royalties. This is where ARM is very smart. They partner with the foundries, so they collect the royalties from either TSMC or UMC. The foundry gives ARM a report, so ARM knows how many wafers have been shipped.

It’s not easy to survive by selling IP, and we don’t sell IP. Our approach, rather, is to share the risks with the customer. We say, “Let’s work together and win together.” That means that when I work with you in putting a chip on the market, I need to have extremely good specifications for the chip, in order to satisfy customer demand. Then if the chip does well in the market, we sell the design to the customer, and both sides make money. This is the business model we prefer to operate.

Q: What is the future for EE Solutions and the industry? Can Moore's Law be sustained, and for how long?

Su: There are two points of view. One is that when you design at the nanometer level, you tend to count on technology provided by others. The foundry, for example, has to invest very large sums in technology for deep submicron, in acquiring the capability to go to 65 and 45 nanometers, and so on. This is from the process point of view. From the design point of view, the problem is that what works today may not work tomorrow at 65 and 45 nanometers. We have to look for a design breakthrough, a breakthrough in design, not simply in the process technology.

That means that the EDA industry can expect to see high levels of growth. There will be a large number of start-ups in the US, all looking at the process from different points of view. For example, I can give you at least ten examples of start-up companies in Silicon Valley who are developing DFM technology. Why? It’s because there is a demand, and the same applies to DFY. Some companies address these issues starting from RTL coding. Other people start from place and route; others start from routing. People are looking at these issues from different points of view, and all this is driven by Moore’s Law, of course.

This poses two major challenges for the industry. One of those issues is scalability. The industry will have to become very scalable. For example, let’s say there are now 500 fabless IC chip-design companies in China. They will inevitably face a lot of consolidation. There are going to be fewer fabless design companies. The second challenge is capital investment. How many companies can afford to continue to invest in fabs and foundries for fabrication at 300mm and 65 nanometers?

Recently I spoke with Princeton Technology Corporation (PTC), a very large company that last year shipped 400 million ICs, although most of those are consumer chips. Now that they are moving to deep submicron, they would be interested in partnering with us, to reduce their investment load. They want to reduce their investment in capital equipment and people, as they move into deep submicron. However, at 90 nanometers, you have to have a complete design team. It’s no longer a process that can be handled by individuals. At 0.35 micron, for example, one person could handle the EDA requirement, but that would not be the case at 90 nanometers.

So I think that on the one hand we will end up with a number of fabless companies, and on the other a number of system companies, whose major focus will be products for consumers. In between, they will need a company such as EE Solutions, which can provide services for both types of company. They will need to leverage our expertise, our resources and our investment. I can’t say exactly when this will happen, but I’m certain this will be the trend.

Q: So you are anticipating growth in the EDA industry?

Su: Yes. There are a lot of new entrants to the EDA industry. The past couple of years have been very slow for the EDA industry, but next year I think you will see a lot of new companies addressing the problems we have been talking about.