Power Integrity Design Flow

• EES Low-Power design flow provides users with a complete front-to-back methodology for low-power implementation and verification platform. It contains low power IPs with low power design methodology for Power Switch, Multi-supply/Multi-voltage, Multi-Vt library and gated clock implementation.
  
  
• Those methodologies help to achieve the lowest leakage/standby/dynamic power.
  
  
• Perform Static IR analysis, Dynamic IR analysis, SSO analysis/prevention

	Static IR/Dynamic IR
	SSO Analysis