Methodology

• EES participate the design quality checking though several state-of-art methodology to insure the best quality of the result chips.
  
  
• The design quality checking includes those: Code purification, netlist checking,
  pin-ball assignment check, design power calculation, cycle-base pattern translator.
  
  
• Several methodologies were deployed to insure the best high-quality and low-cost chips.
  - Power integrity flow: Design for low power
  - Signal integrity flow: Signal integrity effects handling
  - Nanometer design flow: Nanometer physical/electrical handling
  - Optical shrink technology: Cost down by optical shrink process
  - ESD quality check/design: Whole chip ESD protection design methodology