ESD Quality Check/Design

• ESD Protection Design
  - Superior ESD protection design method for I/O cell
   - Superior whole chip ESD protection design methodology
• Design for multi-power domain
• Design for multi-analog/digital domain
• Relationship between ESD level and the distance of power/ground to signal cell
• Design for high speed application
• Design for high voltage tolerance I/O cell
• Embedded clamp circuit
• Good discharge paths