Introduction

Demands for high performance and low cost ICs continue to grow as we step into the deep submicron arena. Goal for meeting “Successful First Tape Out” has becoming difficult to achieve due to the increased design complexity that resulted from the shrinking transistors. The traditional approach of “one company does it all” has caused companies millions of dollars on re-tape-outs if design activities are not executed correctly. Not to mention the loss of business opportunities due to the delayed volume production.

The key ingredients for successful tape outs that enable IC or System Design Houses to meet the time to market pressure are:

• Correctness of design flow/methodology
• Readiness of the reliable processing technologies
• Availability of silicon proven IPs and libraries

EE Solutions has completed and taped out more than 250 designs over the past four years. Numerous designs are in volume production since the early days when the company was founded. The successful completion of these designs requires support from multiple sources of our design partners. We have enduring partnerships with EDA vendors, IP/library vendors, and semiconductor foundries. We believe in the concept of “division of labor” and are actively searching for new partners to meet the continuous design challenges.

By working with multiple design partners, we are able to select the best tools from different tool vendors, best IPs from different IP vendors, and best semiconductor foundries that meet customers' design requirements. We have a unique “hybrid” design environment that uses tools from multiple EDA vendors plus internally developed tools for power, noise and die size optimization. We have taped out designs in TSMC, UMC, CSM, SMIC, etc. to suit customer's design/business requirements. We have vast number of IPs available in numerous process technologies across different foundries. Furthermore, by teaming up with our design partners, we are able to focus on what we do best by offering a complete integration service that enables our customers to deliver high performance solutions in multiple application domains.

Value of ASIC Solution to Customer

    Value to Customer

• Cost Down (IC and BOM)
• Market Differentiation (unique solution)
• Customer Specific Solution (no standard IC or combined IC solutions)
• Product Protection (no off-the-shelf ASIC supplier)
• Product Extension (flexibility)
• Secured ASIC Supply (not dependent on IC supplier)

    EES Service Types

• Provide pin-to-pin compatible solutions
• Provide multiple IC integration solutions
• Provide customized IC solutions

EES Differentiations

• Channel to Systems and IC customers in Greater China Market
• Wide selection of IP Partners and Design Partners for VASIC program
  
• Choices of Testing & Assembly Houses here in Taiwan & China for cost down
• Internal IP development capability
• IO and memory development capability
• Advanced Design Technologies/Methodologies
  - ESD
  - RTL Qualification
  - Hierarchical Design Flow
  - Clock/Power Methodologies
  - Optical Shrink Technology (GDS2GDS design flow)
  - Hybrid Design Flow – SoC Encounter, Magma